1. Technical Field
The present disclosure relates to a semiconductor test system, and particularly to improvements in match detection in which an expected value pattern is compared and collated with an output pattern and then the presence or absence of match between the patterns is detected.
2. Background Art
In a kind of semiconductor test system, there is a system constructed so as to perform match detection. In the match detection, a given test pattern is applied to a device under test (hereinafter referred to as DUT) from a pin electronics (hereinafter called PE) card, then a pattern outputted from the DUT in response to the test pattern is compared with an expected value pattern, and then the presence or absence of a match between these patterns is detected. A pass/fail of the DUT is determined based on a result of the match detection.
FIG. 4 is a block diagram showing a configuration example of a main part in a semiconductor test system according to the related art. A plurality of PE cards 11 to 13 are provided in the semiconductor test system. Pattern generation parts 21 to 23 and match detection parts 31 to 33 are respectively provided in each of the PE cards 11 to 13.
The PE card 11 applies a test pattern to DUTs 1 to 3 from the pattern generation part 21 and also captures patterns outputted from the DUTs 1 to 3 in response to the test pattern. The PE card 12 applies a test pattern to DUTs 3 and 4 from the pattern generation part 22 and also captures patterns outputted from the DUTs 3 and 4 in response to the test pattern. The PE card 13 applies a test pattern to DUTs 5 and 6 from the pattern generation part 23 and also captures patterns outputted from the DUTs 5 and 6 in response to the test pattern.
The match detection parts 31 to 33 provided in each of the PE cards 11 to 13 perform match detection. In the match detection, by using fail information aggregated every DUT in each of the PE cards 11 to 13, output patterns of each of the DUTs are compared and collated with expected value patterns in response to the test patterns outputted from the respective pattern generation parts 21 to 23 and then the presence or absence of match between the patterns is detected.
Based on a match detection result of each of the match detection parts 31 to 33, pattern sequencers (not shown) provided in the pattern generation parts 21 to 23 of each of the PE cards 11 to 13 decide a branch direction of an internal conditional branch command for setting and instructing an expected value pattern or a test pattern to be next outputted in accordance with a test sequence.
JP-A-2003-196999 discloses a semiconductor test system in which a test pattern is applied to a DUT, then a pattern outputted from the DUT in response to the test pattern is compared with an expected value pattern and then the presence or absence of match between these patterns is detected.
By the way, in the block diagram of FIG. 4, the DUT 3 is connected so as to give and receive a signal to and from two systems of the PE card 11 and the PE card 12. In such a test environment, there is a possibility that match detection results of the match detection parts 31 and 32 provided in the PE card 11 and the PE card 12 are different from each other and either of the output patterns of the DUT 3 does not match with an expected value pattern.
When the match detection results of the match detection parts 31 and 32 provided in the PE card 11 and the PE card 12 are different from each other, the pattern sequencers provided in the pattern generation parts 21 and 22 of each of the PE cards 11 and 12 execute mutually different conditional branch commands and instruct different branch directions. In this case, the pattern generation parts 21 and 22 apply different test patterns to the DUT 3, and thus match detection functions of the match detection parts 31 and 32 cannot be performed.